History of the Organization.
We started our journey in August 2020. With vast experience in chip design and EDA software development, we designed our first microprocessor by early 2021. Taped out in 2022 and the engineering samples came in mid 2023.
We contribute heavily in open-source EDA tools. In 2020 completed iLint, a RTL level linting tool and published a paper in CONECCT 2021. Completed iSynth, a technology independent synthesis tool and published a paper in TENSYMP 2023.
Accomplished work.
16-bit processor, DFF RAM, SPI protocol, I2C Protocol, UART, general purpose timer, PWM. Three tape out. Skywater 130 nm and Global Foundry 180 nm.
Academia Relations with KSSEM, BIT and NMIT. Internship of 2 batches of UG students.
The features we offer.
The SoC we are designing are equivalent to Arduino, STM and PIC controllers.
The layout of the first tape out. Only micro-processor. Technology node, 130 nm.
Open-source tool for RTL level linting. Based on iVerilog APIs. Published in CONECCT 2021
The layout of the second tape out. Micro-processor and 4KB RAM. Technology node 130 nm
For testing the SoC. Currently L&L 1
The layout of the 3rd tape out. Twelve micro-processors, 24 KB RAM, 2 SPI and 2 I2C serial channels.
Open-source tool for technology independent logic synthesis. Based on iVerilog APIs. Published in TENSYMP 2023
Customer satisfaction most important.
We don't have any customer yet. Looking for partners in the domain of embedded systems. Our SoC can be used for industrial automation, motor control. Hobbyists can use it for display and robotics.
"Dummy one customer says excellent product and services."
Dummy two customer says excellent product and services."
"Dummy three customer says excellent product and services."